200 MHz System Clock

Stock QMK leaves the RP2040 at the clock the pico-sdk picks at boot. PolyKybd sets it explicitly, because drawing 72 keycap displays and decompressing overlay images is compute-bound work that scales with the clock.

The firmware runs the RP2040 at 200 MHz, and has done since v0.11.0. Raspberry Pi certified the chip for that in 2025; it is a supported operating point, not an overclock — but only with the core voltage raised from 1.10 V to 1.15 V, so the build does both: it selects the 200 MHz PLL setting and raises the regulator before the clock comes up. There is nothing to configure.

If a board ever misbehaves at the higher clock, one flag builds the old one:

qmk compile -kb polykybd/split72 -km default -e POLYKYBD_SYS_CLK=125

That escape hatch is verified byte-for-byte identical to the pre-v0.11.0 firmware, so it is a genuine return to what shipped before rather than a similar-looking rebuild.

Measured on the test rig, against a 125 MHz build on the same hardware:

	change at 200 MHz
Switching applications (overlay upload)	~28% faster — about 74 ms off each switch
Keycap rendering	~30% faster
Idle main-loop rate	~16–24% higher
Typing latency (HID round-trip)	unchanged
Split-link timing	unchanged

Note

The gains land on compute — drawing keycaps, decompressing overlays. Anything bound by a bus or a wire rather than by the processor is unaffected: HID latency is set by the USB frame rate, and traffic to the other half by the fixed UART speed. That is also why the idle loop gains less than the 1.6× clock increase might suggest — roughly half of each idle pass is time on the wire to the other half, which no amount of MHz will shorten.

To confirm what a keyboard is actually running — and that the regulator was raised to match — watch the boot banner on the firmware console. Both values are read back from the hardware rather than assumed from the build flags:

   clk: sys=200000000Hz vreg_vsel=0xC

How the build sets it

QMK never sets the RP2040 clock itself. ChibiOS’s hal_lld_init() calls the pico-sdk clocks_init(), which reads the compile-time SYS_CLK_KHZ, so keyboards/polykybd/rules.mk sets that value. 200 MHz comes from a 1200 MHz PLL VCO divided by 6 and then by 1.

The vendored pico-sdk predates the SDK’s automatic voltage raise and does not compile hardware_vreg. The firmware therefore writes the regulator register itself (POLYKYBD_VREG_VSEL) before the first clocks_init() runs. The patch is listed in UPSTREAM_PATCHES.md under platforms/chibios/bootloaders/rp2040.c.

Peripherals needed no rework. SPI, I2C, the PIO split UART and the WS2812 driver compute their dividers from the live clock_get_hz(clk_sys), and USB runs from its own 48 MHz PLL. The one fixed divider is the XIP flash clock: boot2 runs it at clk_sys / 4, which is 50 MHz at 200 MHz and 31.25 MHz at 125 MHz. Both are well inside the QSPI part’s rating.

Caution

If you add a third clock setting, check the XIP divider again. It is the only divider that does not follow the system clock.